The present invention relates to integrated circuit memory device structures and fabrication methods.
Background: DRAMs
Memory device capacitor structures for gigabit dynamic random access memory (DRAM) applications typically include a bottom storage electrode formed over a polysilicon plug within the interlevel dielectric layer (e.g. silicon dioxide). The polysilicon plug is in contact with an underlying transistor. A dielectric layer that has a high dielectric constant is usually deposited over the bottom storage electrode, which provides the increased capacitance that these structures exhibit. A top electrode, which can be of the same material as the bottom storage electrode, can then be deposited over the resulting stacked cell capacitor structures. Similar architectures can also be used for FRAM (ferroelectric random access memory) cells, if the dielectric is ferroelectric.
Background: High Dielectric Constant Materials
For future memory device capacitor structures, high-dielectric-constant materials such as barium strontium titanate (BST) or ferroelectric materials such as lead zirconium titanate (PZT) are leading candidates for the dielectric material. Such materials have extremely high dielectric constants (possibly greater than 1000). However, care must be taken to avoid formation of a native oxide on the electrode (or other native dielectric layer) which could degrade the benefit of the high-dielectric-constant (high-k) material. The effect of a native oxide would be to add a lower-value capacitor in series with the desired high-value DRAM capacitor, and this would greatly reduce the net capacitance between the plates.
Background: Bottom Electrode Materials
Promising candidates for bottom electrode materials include the eight noble metals (e.g. at least 50 percent atomic of any combination of the following: platinum, palladium, ruthenium, iridium, rhodium, osmium, gold, and silver), and their oxides (such as RuO2, IrO2, Rh2O3, OsO2, and PdO2). These eight metals (of which platinum is the most common) are all physically and chemically fairly similar, and all are quite stable (or form conductive oxides, so the capacitance is not degraded) in oxidizing, reducing, or inert atmospheres at high temperatures. In addition, these materials are resistant to hydrogen damage, and do not degrade the dielectric polarization after annealing at high temperatures.
A particularly important characteristic of DRAM electrode materials is the work function. (This number describes the energy required to remove one electron from the metal.) A dominant leakage mechanism in advanced DRAM cells is Schottky emission from the metal into the dielectric, so metals with a higher work function produce less leakage. Platinum has a notably high work function, and hence is particularly attractive for such applications, but the other noble metals, and their oxides, all have fairly high work functions as well.
Background: Storage Node Structures
In most storage node structures, the bottom electrode material will be in direct contact with silicon dioxide, which serves as the interlevel dielectric between the storage node and the underlying CMOS transistor. A schematic of a simple prior art cell structure, at an intermediate stage of fabrication, is shown in FIG. 3. A barrier layer 340, such as TiAlN, separates the polysilicon plug 330 formed in the interlevel dielectric material 320 (e.g. SiO2) from the bottom electrode 300. A dielectric layer 310 (e.g. BST) is also shown covering the entire structure, including the bottom electrode 300. (In this figure the dielectric layer has not yet been etched, and the under-lying transistor and overlying top electrode are not shown.) The dielectric layer 310 is preferably deposited by chemical vapor deposition (CVD) under oxidizing conditions, but can alternatively be deposited by sputtering.
A lithographic process will typically be used to define the bottom electrode structure, which will have sub-quarter-micron geometries. However, the noble metals which are used in these capacitor structures are difficult to dry etch due to the lack of volatile reaction products.
In addition, a significant problem exists with using a photoresist mask during platinum etching because of the polymer redeposition onto the platinum structure being etched. Removal of this residue can be difficult. It has been found that adding oxygen to the etch chemistry can improve the platinum etching characteristics, but this could severely damage the photoresist during etching.
Moreover, etching these noble metals is difficult because they do not have volatile halogen species. Therefore, a chemically enhanced ion milling etch process is typically used. However, the etch selectivity between the platinum and the photoresist mask is poor, and therefore a thick photoresist mask must be used. In addition, the platinum redeposits onto the sidewalls of the photoresist during the etch process, which results in substantial growth of the feature size dimensions (e.g. approximately 0.5-1.0 times the platinum thickness). For small features, this is unacceptable. Furthermore, when the photoresist is removed, the redeposited platinum remains, which is extremely undesirable. In order to remove the redeposited platinum, a sloped photoresist must be used during the etch. However, a sloped photoresist produces a sloped platinum layer, which is also not desirable, especially for etching small features. Adding oxygen to the etch gas helps the selectivity of platinum to the underlying dielectric, but greatly degrades the selectivity of platinum to the photoresist.
Background: Silica Hardmasks
The use of a hardmask, such as silica (SiO2), instead of a photoresist mask, is desirable for patterning DRAM capacitor electrodes since any residue that forms can be easily removed. However, noble metals adhere poorly to SiO2, and therefore SiO2 would not perform well as a hardmask for these materials without the use of an adhesion promoter. A thin layer of titanium is often used to promote adhesion between SiO2 and metals, but introducing titanium into the electrode material is likely to result in degradation of the capacitor structure. Another conventional method of increasing the adhesion between metals and silica involves the use of thermal silicon oxide. However, while thermal oxide does yield moderate platinum adhesion, it cannot be used in hardmask applications since it is a grown, rather than deposited, material.
Adherent Hardmask Structures and Methods
The present application discloses a process for forming capacitors, which uses silicon nitride as a hardmask to pattern a noble metal electrode. Silicon nitride has been shown to yield improved platinum adhesion as compared to any kind of silicon oxide. The silicon nitride can be deposited by several methods, including low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or Jet Vapor Deposition. Since silicon nitride is oxidation resistant, it resists erosion by oxygen in the etch chemistry. Silicon nitride hardmasks have been previously used as an intermediate hardmask layer in tri-level photoresist processing applications and as a hardmask for patterning oxides and silicon in recessed variants of LOCOS isolation, but not for patterning metals. This etching process can advantageously be used during processing of high-k capacitor structures in DRAMs in the .gtoreq.256 Mbit generations.
Advantages of the disclosed methods and structures include:
Si3N4 dispenses with the need for any adhesion promoter, which both simplifies the processing and results in a more robust capacitor structure; PA0 Si3N4 is a standard semiconductor material with well established properties and processing techniques; PA0 Si3N4 has been shown to yield significantly better platinum adhesion than silicon oxide, and is expected to have similar adhesion characteristics for other materials such as palladium, ruthenium and iridium; PA0 no extra surface treatment is needed to enhance adhesion to platinum; PA0 Si3N4 fulfills the requirements of hardmask material; and PA0 Si3N4 can also be used as an anti-reflection coating for deep UV lithography.